FIGS. 1A-1C illustrate various aspects of graphics processing techniques and how interpolation of vertex parameters may be used to process graphics and render virtual objects in an image. A graphics processing technique may utilize a barycentric interpolation process in order to define parameter values at various locations of the virtual object to be displayed.
By way of example, and not by way of limitation, parameter values may be positions, colors, texture coordinates, lighting, and the like at each vertex of a primitive located in virtual space, and barycentric interpolation of these vertex parameters may be used to determine a parameter value at any location within the primitive. For example, any number of pixels may be located within the primitive when used to render a virtual scene on the pixels of the display, and such interpolation of the vertex parameter values may be used to determine the corresponding parameter value at the pixel location within the primitive.
Illustrative aspects of an interpolation process using a barycentric coordinate system are depicted in FIG. 1A. FIG. 1A depicts a polygon (e.g., a triangle) 102 that can be utilized as a primitive for processing graphics with a GPU. It is noted that triangles are commonly used as primitives in graphics processing as they are the two-dimensional shapes with the smallest number of vertices (three), and each triangle is guaranteed to be planar. The surface of a virtual object, such as a three-dimensional object, in an image to be rendered can be comprised of a large number of triangle primitives 102 oriented in virtual space. The triangle 102 may include vertices 104a, 104b, 104c each having certain parameter values P0, P1, P2, respectively.
By interpolating the vertex parameter values P0, P1, P2, a parameter value Pi,j at any point in the triangle 102 may be defined using a linear relationship between the parameters at the corners of the shape. The coordinates i,j may correspond to the locations of a pixel (or pixel center) when the image having the virtual object is rendered in screen space on a display. Accordingly, this interpolation process may be used to determine the parameter value for any of the pixels located in the primitive 102. In any given triangle 102 of a virtual object, there may be any number of pixel centers located within the triangle. For example, there may be zero, one, ten, or more pixels located within the primitive.
In order to interpolate the vertex parameters at location i,j, one of the vertex parameter values is subtracted out from the parameter values of the other vertices, and these subtracted values are multiplied by each of the barycentric coordinate positions within the triangle 102 corresponding to the desired parameter value's location. This can be expressed mathematically as follows, in which the vertex parameter P0 is subtracted out from the other two vertex parameters P1, P2, and these subtracted values are multiplied by the corresponding coordinate values i,j:Pi,j=P0+(P1−P0)i+(P2−P0)j 
FIG. 1B depicts a plurality of triangles 102a-d similar to triangle 102 of FIG. 1A which may be used to render a virtual object for a graphics processing application. FIG. 1B and the description below is a simplified schematic description in order to illustrate various aspects of how vertex parameter data is utilized and stored when implementing graphics processing techniques.
Each of the triangles 102a-d has three vertices which may each have corresponding parameter values. Moreover, the triangles 102a-d share many common vertices and, as such, many of the parameter values are common to different triangles. Rather than storing the parameter values multiple times so that they are associated with each of the triangles, each vertex may be assigned an identifying index. By way of a simplified example, the vertices shown in FIG. 1B are each assigned the identifying indices 0, 1, 3, 9, 10, 4. These indices and their associated parameter values may be stored in what is commonly known as a “vertex buffer.” Moreover, each of the triangles 102a-d may be identified by their corresponding vertex indices, e.g., triangle 102a may be identified by (0,1,3), triangle 102b may be identified by (1,3,9), and so forth, and this information may be stored in what is commonly known as an “index buffer.” Accordingly, the common vertex parameter values may be associated with each distinct triangle 102a-d through the respective indices identified in the buffers.
FIG. 1B also depicts a series of pixel locations a-f overlaid over the primitives 102a-d. Interpolation of the parameter values, e.g., as discussed above with reference to FIG. 1A may be used to determine a parameter value at each of the pixel locations a-f within each primitive based on each vertex parameter values and the indices identifying each primitive. By way of example, and not by way of limitation, the triangles 102a-d may be oriented in a three-dimensional virtual environment, and the pixel locations a-f may correspond to the pixels of a two-dimensional screen used to display an image of the rendered virtual environment.
FIG. 1C depicts the triangles 102a and 102b of FIG. 1B in order to illustrate various aspects of how parameter values may be assigned to the pixels a, b, c located within the triangles. As shown in FIG. 1C, the vertex parameter values P0, P1, P2 may be uniquely assigned for each distinct triangle 102a, 102b, and identified based on the indices 0, 1, 3, 9 stored in the index buffer. Interpolation can be performed by access the corresponding parameter values from the vertex buffer and subtracting parameter value P0 from the remaining vertex parameters P1, P2, e.g., as described above with reference to FIG. 1A.
As an alternative to interpolating parameter values of each primitive, a technique known as “flat-shading” may be used. With flat-shading, a “provoking vertex,” e.g. P0, may be defined for each triangle and the differences to the remaining vertices, e.g., P1−P0 and P2−P0, are then simply zeroed out. Any pixels located within the triangle are output from the vertex shader with the parameter value of the provoking vertex. This can save significant overhead associated with the interpolation computations; however, it may result in a faceted look for the virtual object, which may be undesirable in many applications.
In FIG. 1D, a flow diagram is depicted illustrative various aspects of performing interpolation of vertex parameters in accordance with one traditional method 100a, whereby the entire interpolation is performed before being received by the pixel shaders. The method 100a of FIG. 1D utilizes the triangles 102a-d as depicted in FIGS. 1B and 1C in order to illustrate how the vertex parameters are interpolated in coordination with vertex shaders 110 and pixel shaders 112 in order to determine parameter values for pixels a-f (it is noted that a-f may be more accurately referred to as fragments or pre-pixels, as further modification may be performed by the pixel shaders before outputting them to a frame buffer, but they are simply referred to herein as pixels for purposes of explanation).
The method 100a may include performing certain vertex shader computations 114 with the vertex shader 110, which may include certain manipulations of the vertex parameters of a virtual object on a per-vertex basis according to draw commands received from a graphics API that coordinates rendered graphics with an application's virtual environment. The vertex shader 110 may output corresponding vertex parameter values P0, P1, P2 for each of the triangles 102a-d as shown in FIG. 1D.
These vertex parameter values P0, P1, P2 are interpolated at 116 for each triangle in order to determine parameter values Pa-Pf at pixel locations a-f located within the corresponding triangles 102a-d. Interpolation at 116 includes subtracting out vertex parameter P0 and from the other two vertex parameters P1, P2, multiplying these subtracted values by their corresponding barycentric coordinates, and adding the multiplied values to interpolate the parameters at the pixel locations as defined by the coordinates, e.g., as described with reference to FIG. 1A. In the technique depicted in FIG. 1D, the interpolation 116 is performed entirely by a parameter interpolation hardware component associated with a GPU before the pixel shader program 112 receives the parameter values as an input. The pixel shader 112 may further manipulate each pixel a-f by performing certain pixel shader computations at 118 on each of the pixels a-f, i.e., on a per-pixel basis, resulting in output pixels 120, which may then be stored in a frame buffer and can be output as a rendered image on a display.
In FIG. 1E, an alternate flow diagram is depicted illustrative various aspects of performing interpolation of vertex parameters in accordance with another traditional method 100b. The traditional method 100b depicted in FIG. 1E is similar to the traditional method 100a of FIG. 1D, except that only the subtraction portion 122 of the interpolation 116 is performed before the parameters reach the pixel shader 112. In this technique 100b, this subtraction portion 122 of the interpolation 116 is performed by a parameter interpolation hardware component associated with a GPU before the pixel shader program 112 receives the subtracted parameter values as an input and performs the remainder of the interpolation 116. Accordingly, the remainder of the interpolation 116 of the vertex parameters can be reduced to a simple multiply and add operation at 124 of the absolute vertex parameter P0, the subtracted parameter values P10, P20 subtracted relative to the parameter P0, and the coordinates of the desired parameter P relative to the absolute vertex parameter P0, whereby P10=P1−P0 and P20=P1−P0 for each of the corresponding triangles 102a-d. This results in the desired parameter values Pa-Pf as before, which can then be further manipulated with the pixel shaders at 118 to generate output pixels 120.
FIG. 2A depicts a schematic of a method 200a implemented with various hardware and software components configured to process graphics in accordance with a traditional method.
The method 200a depicted in FIG. 2A is similar to the method 100b depicted in FIG. 1E.
The vertex shader 210 may perform various vertex shader computations 214 that include determining positions 230 of vertices of the primitives in screen space and various other rendering effects 234 on the vertices of each primitive, such manipulating the lighting, shadows, colors, and the like, of the vertices. The various parameters P0, P1, P2 resulting from the vertex shader computations 214 may be written to a parameter cache 236 for temporary storage, and a parameter interpolation hardware component 222 of the system may perform part of the interpolation by subtracting the parameter values before writing respective sets of parameters from the parameter cache 236 to each small local memory unit 237 of each compute unit of a GPU. Each local memory unit 237 may be a small but fast local memory unit sometimes known as a local data share (LDS) associated with each compute unit of a GPU, and there may be a plurality of such memory units and compute units running shader programs in parallel.
The vertex shader output positions 230 may be used by a hardware component 238 that generates barycentric coordinates i,j of pixels relative to each primitive so that they may be used to interpolate parameter values, e.g., as described herein. The pixel shader 212 may access the absolute parameter value P0 and the relative parameter values P10, P20 from the local data share 237 in order to complete the interpolation by performing multiply and add operations 224 using the coordinates of each desired parameter i,j. The pixel shader 212 may then perform certain further pixel shader computations 218 to further manipulate the pixels before outputting them, e.g., to a frame buffer.
One drawback with the technique 200a described above is that certain bottlenecks associated with throughput of the parameters to the pixel shaders may occur, which may slow down the speed of rendering virtual objects. For one, it has been recognized that the parameter write throughput to the parameter cache results in bottlenecks. For example, each parameter may be a large attribute variable, such as, e.g., a 32-bit floating point number, and the vertex shader may write these attribute variables to the parameter cache 236 as a series of wavefronts, e.g., 4 at a time. Moreover, the parameter cache usage may further limit the number of vertex shader wavefronts that may be stored, creating additional bottlenecks. The parameters are then copied to the local data share 237 and temporarily stored before being accessed by the pixel shaders, and the limited throughput and total local data share usage can again create bottlenecks by limiting the number of pixel shader wavefronts.
Another drawback with the technique 200a described above is that, because the subtracted parameter values P10, P20 are calculated before reaching the pixel shader 212, the pixel shaders do not have direct access to the raw parameter values P1, P2, thereby limiting the types of rendering effects that can be performed with the pixel shaders.
Implementations
A graphics processing technique 200b according to various aspects of the present disclosure is depicted in FIG. 2B. In the illustrated technique 200b, compression scheme may be utilized in order to minimize bottlenecks associated with the throughput of parameter values output from vertex shaders. It is noted that although this example is described in terms of primitives in the form of triangles, the concept may be readily expanded to primitives based on other types polygons.
One challenge is that vertex parameter values cannot simply be compressed because traditional methods are configured to perform some or all of the interpolation before reaching the pixel shaders. As a result, the subtraction may prevent the original compressed values from being decompressed for use by the pixel shaders.
By way of example, and not by way of limitation, where the parameter values are stored as 32-bit floating point attribute variables, it may not be possible to compress the parameter into 16-bit numbers for storage into one 32-bit value without losing the original data as a result of the 32-bit subtraction. The following example illustrates the problem using ordinary numbers to conceptualize the problem:                First triangle: {P0, P1, P2}={8, 5, 6}        Second triangle: {P0, P1, P2}={1, 4, 7}        
Subtraction of the parameter values for interpolation, e.g., as performed by the difference engine described above with respect to FIG. 2A, would be:                First triangle: {P0, P10, P20}={8, (5-8), (6-8)}={8, −3, −2}        Second triangle: {P0, P10, P20}={1, (4-1), (7-1)}={1, 3, 6}        
Compressing the first set of parameters with the second set of parameters would be analogous to putting them together as follows:                Compressed parameters: {18, 45, 76}        
And subtraction of the compressed parameters would be analogous to:                Subtraction: {18, (45-18), (76-18)}={18, 27, 58}        
As compressed, the subtraction destroys the original data because the subtraction results 27, 58 are essentially meaningless with respect to the true parameter values. As such, values cannot be decompressed and the original P10, P20, or P1, P2 cannot be recovered from the subtraction results.
Turning again to FIG. 2B, the technique 200b includes a compression scheme according to various aspects of the present disclosure that allows for the original parameter values to be preserved and decompressed so that they may be accessed by the pixel shader. In the illustrated implementation, parameter interpolation hardware that traditionally performs the subtraction or entire interpolation may be omitted, disabled, or bypassed so that the parameter values may be compressed and decompressed without losing the original parameter values.
In the technique 200b depicted in FIG. 2B, the vertex shader 210 may perform vertex shader computations 214, which may include manipulating various parameters of each vertices in the image. The resulting parameters may be compressed at 240 into a smaller data format so that bottlenecks associated with storage and throughput of large numbers may be minimized. The compressed parameters P0′, P1′, P2′ may be written to a parameter cache 236 for temporary storage, and may occupy a smaller amount of the total cache than uncompressed parameters to thereby minimize potential bottlenecks in the cache hardware. The compressed parameters P0′, P1′, P2′ may be copied to a local memory unit 237 on a GPU, which may be memory unit known as a “local data share” (LDS). The compressed parameter values may be accessed from the local data share with a pixel shader 212 implemented by a GPU.
The compressed parameter values P0′, P1′, P2′ may be decompressed at 242 by the pixel shader 212, thereby granting access to the raw parameter values P0, P1, P2 by the pixel shader. The pixel shader 212 may then interpolate the parameter values at 216 using coordinates i,j obtained from the barycentric coordinate generator 238 in order to determine corresponding parameter values at the pixel locations within each primitive. Because the pixel shader 212 has access to the raw parameter values for each vertex of each triangle, the pixel shader 216 may also perform certain other manipulations of the vertex parameters (not pictured) and the visuals of the vertices in virtual space on a per-pixel basis before interpolation 216 to translate the values to screen space. The pixel shader may then perform pixel shader computations 218 to further manipulation of the pixel data and the visuals of the pixels before outputting the final pixel data, e.g., to a frame buffer.
Accordingly, in the illustrative implementation 200b, bottlenecks associated with the large amounts of parameter value data may be minimized or avoided by a compression scheme that reduces total used of the cache 236 and local memory 237. Moreover, programmers creating pixel shader programs may have increased control because they have access to the raw vertex parameter data, not just the relative or interpolated values.
The flow diagram shown in FIG. 3 illustrates a method 300 for processing graphics with vertex shaders and pixel shaders according to various aspects of the present disclosure. The method 300 has similarities to the graphics processing technique 200b depicted in FIG. 2B.
The illustrative method 300 includes performing vertex shader computations 314 with a vertex shader 310. The vertex shader computations may include manipulating various vertex parameters of the primitives 302a-d to produce various visual effects on the vertices in virtual space. The primitives 302a-d may be similar to the triangles 102a-d in FIG. 1B, and each triangle may have corresponding parameter values P0, P1, P2 for each vertex.
The vertex shader 310 may then compress the parameter values and send the compressed vertex parameter values P0′, P1′, P2′ to the pixel shader 312. The pixel shader may then decompress the parameter values at 342 to get the original raw parameter values, and the pixel shader 312 may perform the entire interpolation 316 of the parameter values P0, P1, P2 to determine the corresponding parameters Pa-Pf of each pixel. The pixel shader 312 may then produce additional visual effects on the pixels by performing pixel shader computations 318 on the pixels with interpolated parameter values, and may output the rendered pixels 320, e.g., to a frame buffer in system memory.
Aspects of the present disclosure include graphics processing systems that are configured to implement the features discussed above. By way of example, and not by way of limitation, FIG. 4 illustrates a block diagram of a computer system 400 that may be used to implement graphics processing according to aspects of the present disclosure. According to aspects of the present disclosure, the system 400 may be an embedded system, mobile phone, personal computer, tablet computer, portable game device, workstation, game console, and the like.
The system 400 generally may include a central processor unit (CPU) 470, a graphics processor unit (GPU) 471, and a main memory 472 that is accessible to both the CPU and GPU. The CPU 470 and GPU 471 may each include one or more processor cores, e.g., a single core, two cores, four cores, eight cores, or more. The main memory 472 may be in the form of an integrated circuit that provides addressable memory, e.g., RAM, DRAM, and the like.
By way of example, and not by way of limitation, the CPU 470 and GPU 471 may access the main memory 472 using a data bus 476. In some cases, it may be useful for the system 400 to include two or more different buses. The main memory 472 may contain data that can be accessed by the CPU 470 and GPU 472. The main memory may temporarily store buffers of data, which may include vertex buffers 463, index buffers 466, and frame buffers 464.
The CPU may be configured to execute CPU code, which may include an application 460 utilizing rendered graphics, a driver/compiler 461 and graphics API 462 for issuing draw commands to programs implemented by the GPU. The CPU code may also implement physics simulations and other functions. The GPU may be configured to operate as discussed above with respect illustrative implementations of the present disclosure. In particular, the GPU may execute GPU code, which may implement vertex shaders 410 and pixel shaders 412, as discussed above. The shaders may interface with data in the main memory 472 and the pixel shaders may output rendered pixels in the frame buffer 464 for temporary storage before being output to a display. The GPU may include a plurality of compute units (CU) 465 configured to perform graphics processing tasks in parallel. Each compute unit may include its own dedicated local memory store, such as a local data share (LDS) 437 described above. The system 400 may also include a cache 436 for temporarily storing compressed vertex parameter data 468, and data may be copied from the cache 436 to each LDS 437, which may then implement shader programs that utilize the data in parallel. The parameter cache 436 may be integrated with the GPU, or may be distinct from the GPU and accessible to the GPU, e.g., via the bus 476. The GPU may also execute other programs, such as, e.g., geometry shaders and compute shaders.
The system 400 may also include well-known support functions 477, which may communicate with other components of the system, e.g., via the bus 476. Such support functions may include, but are not limited to, input/output (I/O) elements 479, power supplies (P/S) 480, and a clock (CLK) 481.
The apparatus 400 may optionally include a mass storage device 484 such as a disk drive, CD-ROM drive, flash memory, tape drive, or the like to store programs and/or data. The device 400 may also include a display unit 486 and user interface unit 488 to facilitate interaction between the apparatus 400 and a user. The display unit 486 may be in the form of a flat panel display, cathode ray tube (CRT) screen, touch screen, or other device that can display text, numerals, graphical symbols or images. The display 486 may display rendered images 487 processed in accordance with various techniques described herein. The user interface 488 may include a keyboard, mouse, joystick, light pen, game controller, or other device that may be used in conjunction with a graphical user interface (GUI). The system 400 may also include a network interface 490 to enable the device to communicate with other devices over a network. The network may be, e.g., a local area network (LAN), a wide area network such as the internet, a personal area network, such as a Bluetooth network or other type of network. These components may be implemented in hardware, software, or firmware, or some combination of two or more of these.
While the above is a complete description of the preferred embodiment of the present invention, it is possible to use various alternatives, modifications and equivalents. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claims, along with their full scope of equivalents. Any feature described herein, whether preferred or not, may be combined with any other feature described herein, whether preferred or not. In the claims that follow, the indefinite article “A”, or “An” refers to a quantity of one or more of the item following the article, except where expressly stated otherwise. The appended claims are not to be interpreted as including means-plus-function limitations, unless such a limitation is explicitly recited in a given claim using the phrase “means for.”